DC Circuit Analysis

Dividing 12 V into 6 V using two equal resistors, but dropping to only 4 V when a load is connected, does not violate the voltage divider formula: the load has changed the circuit. To analyze such problems, one must shift from "memorizing formulas" to identifying ports, writing equations, and determining which relationships are preserved by simplified models. This article uses the same voltage divider to illustrate loading effects, nodal analysis, Thevenin equivalents, and RC transients.

Basic symbols and KCL/KVL are covered in Basic Physical Quantities and Laws. The following assumes ideal linear resistors and sources; non-linear devices require separate modeling.

Why Voltage Dividers Fear Loads

R₁ connects the ideal input voltage Vin to output A, and R₂ connects A to the reference ground. With no load, the two resistors are in series, so Vout = Vin·R₂/(R₁+R₂). After connecting R_L to the output, the lower arm becomes R₂∥R_L, and R₂ in the formula must be replaced by this parallel value.

Take Vin = 12 V, R₁ = R₂ = 10 kΩ. The no-load current is 0.6 mA, and the output is 6 V; after connecting R_L = 10 kΩ, the lower arm becomes 5 kΩ, the total current becomes 0.8 mA, and the output drops to 4 V. The two paths in the lower arm each carry 0.4 mA, which sums to the 0.8 mA in the upper arm.

"R_L should be much larger than R₂" is a rough sufficient condition; a more accurate scale is the output equivalent resistance R_th = R₁∥R₂. The ratio of voltage drop after loading compared to no-load is R_th/(R_th+R_L). If the drop is allowed to be no more than 1%, then R_L ≥ 99R_th is required; in this example, at least 495 kΩ. This is only the static loading error budget, not yet including resistor tolerance, input voltage fluctuation, and input leakage.

Increasing the divider resistors can reduce static power consumption but increases the output resistance, making leakage and capacitor charging effects more pronounced. Therefore, voltage dividers are suitable for proportional sampling or biasing under limited conditions and cannot naturally serve as stable power supply outputs. When connecting to switch-sampled inputs, one must also check the settling time of the sampling capacitor, not just the nominal input resistance.

Current division also stems from the same node relationships: two positive resistors in parallel share the same voltage, I₁/I₂ = R₂/R₁, so I₁ = I_total·R₂/(R₁+R₂). Finite positive resistance branches usually have current; current does not "only choose the path of least resistance."

Nodal and Mesh Analysis: Translating Connections into Equations

Nodal Analysis: Select Unknown Potentials First

In this example, only node A is unknown. The sum of currents flowing out of A through each branch is zero:

(V_A − 12)/10k + V_A/10k + V_A/10k = 0.

Multiplying by 10k gives 3V_A − 12 = 0, so V_A = 4 V. The first term is negative, indicating that current actually flows into A through that branch, not that the formula is wrong. Generally, for a resistive branch between two nodes, the reference current from A to B is (V_A−V_B)/R.

If an ideal voltage source connects a node to the reference ground, that node's potential is directly known. If it bridges two unknown nodes, they can be combined into a supernode; write KCL for the outside, and add the constraint of the voltage difference between the two nodes. Do not directly substitute "resistance equals zero" for an ideal voltage source into a division, creating a division-by-zero error.

Mesh Currents are Calculation Variables, Not Equal to Every Branch Current

Define clockwise mesh currents i_a and i_b for the two windows in the diagram. The left mesh contains the source, R₁, and R₂; the right mesh contains R₂ and R_L. On the shared R₂, the two mesh directions are opposite, so the downward branch current is i_a−i_b.

The corresponding equations are:

• (R₁+R₂)i_a − R₂i_b = 12；
• −R₂i_a + (R₂+R_L)i_b = 0。

Substituting the three 10 kΩ values gives i_a = 0.8 mA, i_b = 0.4 mA; the current in R₂ is 0.4 mA, consistent with the nodal analysis result. Mesh analysis organizes equations for the meshes of planar circuits; when mesh boundary current sources are present, supermeshes and current constraints may be needed. Which method to choose mainly depends on which has fewer unknowns and constraints; there is no need to use both methods simultaneously every time.

Superposition: Turning Off Independent Excitations, Preserving Network Relationships

In linear circuits, the voltage or current response caused by each independent source can be calculated separately and then added according to their signs. An independent ideal voltage source is set to zero by becoming a short circuit, and an independent ideal current source is set to zero by becoming an open circuit; series or parallel resistances in real source models are still retained. Dependent sources depend on circuit variables and cannot be arbitrarily turned off like independent sources. MIT: Circuit Abstractions and Superposition

Consider another simple node N: it connects to 12 V, 6 V, and ground via three 10 kΩ resistors respectively. The nodal equation is (V_N−12)/10k + (V_N−6)/10k + V_N/10k = 0, yielding V_N = 6 V. When only the 12 V source is retained, the contribution is 4 V; when only the 6 V source is retained, the contribution is 2 V, and the sum is still 6 V.

However, the actual power dissipated by the ground resistor is 6²/10k = 3.6 mW. Adding the powers from the two separate results gives only 4²/10k + 2²/10k = 2 mW, missing the cross terms from the square expansion. The correct approach is to superimpose the desired voltage or current first, and then calculate the power.

Linear dynamic responses of capacitors and inductors can also use superposition, but the contribution of initial energy storage must also be handled. Non-linear processes such as diode rectification generally cannot be added source-by-source directly; only local models obtained via small-signal linearization have corresponding applicable scopes.

Thevenin and Norton: Replacing Only the Port Appearance

Remove the load and look into the original divider from A and ground. The open-circuit voltage V_th = 6 V; after setting the independent 12 V ideal source to zero, looking into the port, both 10 kΩ resistors are grounded, so R_th = 5 kΩ. The original network can be equivalent to a 6 V voltage source in series with 5 kΩ at this port.

Let the load draw current I from the port; the port relationship is V = V_th − IR_th. After connecting R_L, I = V_th/(R_th+R_L), and the port voltage is V_th·R_L/(R_th+R_L). It reproduces the previous 4 V without requiring knowledge of how the current divides in the internal branches of the original network after each load change.

The Norton form is a current source I_N = V_th/R_th = 1.2 mA in parallel with 5 kΩ, with the direction chosen to supply current to the output node. When the port is shorted, all current flows through the short; when open, the current flows through the parallel resistor, generating 6 V. The short-circuit current here is calculated from the ideal model and does not require performing a short-circuit measurement on a real source.

How to Find Equivalent Resistance with Dependent Sources

Keep the dependent sources, set only the independent sources to zero, apply a test voltage or test current at the port, and then find R_th = V_test/I_test; take the current direction as entering the network. Dependent sources can change the port resistance; one cannot simply do series-parallel calculations on visible resistors. MIT: Port Equivalent Example with Dependent Sources

These equivalents require that the port relationship can be represented by the corresponding finite parameters. Limiting forms such as ideal current sources and ideal voltage sources may not be interchangeable with finite parameters of the other source type; the equivalent resistance of active networks may also not be positive. DC resistance equivalents cannot directly replace the full time-domain behavior of circuits with energy storage elements; for sinusoidal steady state, impedance corresponding to the frequency must be used, and for transients, initial conditions must be retained.

Maximum Power, Efficiency, and Input/Output Impedance

For a fixed V_th, positive R_th, and variable positive resistance load, P_L = V_th²R_L/(R_th+R_L)², which is maximum when R_L = R_th. In this example, with R_L = 5 kΩ, the load voltage is 3 V, and P_L = 1.8 mW.

In the model of "ideal source in series with actual dissipative resistance," the series resistor and the load dissipate equal power at this point, resulting in an efficiency of 50%. Port equivalents do not preserve internal power dissipation of the original network, so this 50% cannot be taken as the actual efficiency of any arbitrary complex network. For example, in the original divider of this example under this load, the source current is 0.9 mA, input power is 10.8 mW, and the load receives only 1.8 mW, making the actual ratio 1/6.

Input resistance describes the loading on the preceding stage, and output resistance describes the variation of the output with the load; in dynamic scenarios, input/output impedance should be used. Ideal voltage amplifiers often take high input and low output impedance, while current amplifiers often take low input and high output impedance; this is the model goal for port types, not a unified design rule for all amplifier circuits.

Where do source and load agree?

Set RL to 5 kΩ for maximum load power in this model. Compare the efficiency readings: load power agrees while internal input power differs. Identical terminal curves do not establish internal equivalence.

$$V=V_{th}-I{R}_{th}=I{R}_L,P_L=\frac{V_{th}^2{R}_L}{(R_{th}+R_L{)}^2}$$

RC Transients: Find Initial and Final Values First, Then the Resistance Seen by the Capacitor

Connect a capacitor C = 100 nF to the output of the original divider, assuming it is initially uncharged, and connect the 12 V input at t = 0. With no R_L, the Thevenin source seen by the capacitor is 6 V and 5 kΩ. Since the resistor current equals the capacitor current, C·dv/dt = (6−v)/5k; the rate of change is proportional to "how far it is from the final value," thus approaching exponentially.

A more general first-order response is written as: v(t) = v∞ + (v₀−v∞)e^(−t/τ), where τ = R_seen C. Here v₀ is the initial capacitor voltage after switching; in ordinary RC circuits without impulse currents, it equals the voltage before switching. v∞ is the steady-state value of the circuit after switching, and R_seen is the equivalent resistance seen from the capacitor port, calculated by setting independent sources to zero and retaining other components. OpenStax: RC Circuits

With no load, τ = 0.5 ms, v∞ = 6 V. If R_L = 10 kΩ is connected to the output from the start, v∞ becomes 4 V, and R_seen = 10k∥10k∥10k = 10k/3 Ω, so τ ≈ 0.333 ms. One cannot simply change the final value and still use the original RC.

After 1τ, about 63.2% of the difference between the initial and final values is completed; after 5τ, the remaining error is about 0.674%, not completely charged. If the remaining error is required to be no more than ε of the initial difference, the wait time must be at least −τ ln ε. 1% corresponds to about 4.605τ, and the loaded example requires about 1.535 ms. For any initial value, "completing 63.2%" describes the proportion of difference eliminated, not necessarily 63.2% of the final value itself.

When there are multiple independent energy storage states, non-linear components, or time-varying parameters, there may not be just one time constant. After disconnecting the power source, R_seen must be recalculated based on the actual discharge path; one cannot assume it still passes through the original series resistor.

from fractions import Fraction as F
from math import exp, log, isclose
vin, r1, r2, rl = F(12), F(10000), F(10000), F(10000)
vth, rth = vin*r2/(r1+r2), 1/(1/r1+1/r2)
vl = vth*rl/(rth+rl)
assert (vth, rth, vl) == (6, 5000, 4)
assert (vin-vl)/r1 == vl/r2 + vl/rl
assert vth/rth == F(12,10000)
assert (F(4)+F(2))**2/10000 != F(4)**2/10000 + F(2)**2/10000
cap = 100e-9
tau = float(1/(1/rth+1/rl))*cap
settling = -tau*log(.01)
assert isclose(exp(-settling/tau), .01)
assert isclose(float(vl)*(1-exp(-settling/tau)), 3.96)
print(f"Equivalent and nodal forms are consistent; 1% settling time {settling*1000:.6f} ms")

What does each time constant remove?

Start above the final voltage: the same error law describes a falling curve. Adding the load changes 6 V to 4 V and 0.5 ms to about 0.333 ms. If initial and final values coincide, actual error is zero; the displayed exponential is only the decay factor.

$$v-v_{\infty }=(v_0-v_{\infty })e^{-t/\tau },t_{\epsilon }=-\tau \ln \epsilon$$

Δ–Y Transformation: Memorize Formulas by Terminal Names

When a network cannot be directly series-parallel reduced, a three-terminal resistor network can sometimes be converted. Define the three sides of the triangle as R_AB, R_BC, R_CA; the star has three arms from center O to A, B, C as r_A, r_B, r_C. The names directly refer to the terminals, avoiding graphical memory errors of "which resistor is opposite."

Let S = R_AB + R_BC + R_CA. For triangle-to-star conversion:

For the reverse, let P = r_A r_B + r_B r_C + r_C r_A, then R_AB = P/r_C, R_BC = P/r_A, R_CA = P/r_B. The denominator is the star arm opposite to the sought triangle side.

For example, if each side of the triangle is 3 Ω, the equivalent star has each arm as 1 Ω. With the C terminal externally open, the original network between A–B is 3 Ω in parallel with 6 Ω, equal to 2 Ω; the star is two 1 Ω resistors in series, also 2 Ω. What is preserved is the relationship between the three external terminals, not the current or dissipation of each internal resistor.

At the end of the analysis, at least substitute the answer back into one nodal equation and one loop equation of the original circuit. Port equivalents are convenient for calculation, but power, local heating, and component ratings in the original network must still be verified in the original connections. The next article Resistors continues to extend ideal R to actual device parameters.