Power Supply Circuits

"12 V to 5 V, 2 A output" only specifies part of the requirements. How low the input can drop, how fast the load changes, the allowed ripple, whether heat can be dissipated, and how to exit during a short circuit all influence circuit selection. Power supply design must simultaneously satisfy average energy, transient energy storage, and control stability.

Draw the Power Tree First, Then Select Single-Stage Topology

Mains transformer, rectification, filtering, followed by linear regulation is one type of AC input structure; offline switch-mode power supplies can also first rectify to form a bus, followed by high-frequency conversion and the required isolation. Not all AC-DC converters go through a mains transformer first, nor do all power supplies have isolation.

Board-level systems are often powered by adapters, buses, or batteries providing DC input, which then generate different voltages via Point-of-Load (POL) converters. Sensitive analog branches can use an appropriate LDO after the front-end switch-mode power supply, but its effectiveness depends on the LDO's rejection capability at that frequency and voltage drop; relying solely on a two-stage structure does not guarantee low noise.

Record the normal/transient input range, output voltage tolerance, average/peak load, allowed noise, and power-on sequence for each rail. The efficiency of multi-stage conversion multiplies, and currents are converted according to their respective voltages and powers; you cannot simply sum all output currents to determine bus current.

Linear Regulator Energy Accounting

Linear regulators maintain the output by adjusting the series pass transistor via feedback, changing the voltage drop within the required range. "Linear operation" here refers to continuous dissipation adjustment and should not be mechanically mapped to the named operating regions in all transistor textbooks.

Ignoring other power paths, if the input current is $I_{out}+I_g$, the efficiency is $\eta =V_{out}{I}_{out}/[V_{in}(I_{out}+I_g)]$; it approximates $V_{out}/V_{in}$ only when the load is much larger than the ground current. Internal losses are approximately $(V_{in}-V_{out})I_{out}+V_{in}{I}_g$.

For 12 V to 5 V at 0.5 A, the pass transistor dissipates 3.5 W just from the voltage drop, while the output power is 2.5 W, resulting in an idealized efficiency of about 41.7%. Conversely, for 3.6 V to 3.3 V at 100 mA with a 10 μA ground current, efficiency is about 91.7%; linear power supplies do not always have 30%–60% efficiency. At light loads, the proportion of ground current increases, which may change the result. Analog Devices: LDO Basic Concepts

Dropout is an Operating Condition, Not a Fixed Label

An LDO's minimum dropout voltage depends on load, temperature, pass transistor structure, and detection conditions. To ensure regulation, check that the minimum instantaneous input remains higher than the required output upper limit plus the corresponding dropout, accounting for trace voltage drops and ripple valleys. Near dropout, output accuracy and PSRR may already be compromised; do not rely solely on average input being sufficient.

For example, if the output upper limit is 3.333 V and the dropout is guaranteed to be 0.2 V at this operating point, the input needs to be at least ~3.533 V; if the input valley is only 3.5 V, regulation cannot be guaranteed based on this. Whether additional headroom is needed to meet noise or rejection specifications should be checked against the corresponding curves. Analog Devices: Low Dropout and PSRR

LDOs do not generate periodic pulses from power switching nodes, but they still have their own noise, input disturbance coupling, output network, and layout issues, so they cannot be called "EMI-free." Output capacitors and ESR can also affect loop stability; specific requirements should be found in the device documentation, rather than assuming "LDOs work with any low ESR capacitor."

Complete Buck Numerical Derivation

Below is the ideal topology for a non-synchronous Buck. When the main switch is on, energy is transferred from the input to the output through the inductor, and the diode is reverse-biased; when off, the inductor freewheels through the diode, and current continues to flow to the load. The output capacitor current is always determined by $i_C=i_L-I_{load}$; it is not true that the entire load is powered solely by the capacitor during the main switch on-time.

In Continuous Conduction Mode (CCM), steady state, with small output ripple and ignoring losses, the inductor voltage is $V_{in}-V_{out}$ during on-time and $-V_{out}$ during off-time. The net current change over a period is zero, so $D(V_{in}-V_{out})+(1-D)(-V_{out})=0$, yielding $V_{out}=D{V}_{in}$.

Taking $V_{in}=12$ V, $V_{out}=5$ V, $I_{out}=2$ A, $f=500$ kHz, $L=10$ μH:

The valley current is still greater than zero, consistent with the CCM assumption here. The ratio of $\Delta I$ to load can serve as a design entry point, but low load, input extremes, minimum inductance, and current limit thresholds still need to be checked separately. The inductor's peak constraint and RMS thermal constraint are different; see Inductors and Transformers for details.

Capacitor Ripple and Transient are Two Separate Budgets

Under the conditions of triangular inductor ripple, constant load, and simplified ESR/ESL, the ideal capacitor's periodic ripple peak-to-peak is approximately $\Delta I/(8fC)$. If the effective $C=47$ μF at the operating point, this yields ~3.10 mV; with ESR=20 mΩ, the corresponding ESR ripple is approximately $\Delta I\cdot ESR=11.67$ mV.

Adding these two directly to get ~14.77 mV serves as a conservative estimate entry, but the extrema of the two waveform components do not necessarily occur at the same time, nor does it include ESL spikes and control mode effects. In practice, use effective capacitance and ESR curves, not just nominal μF values.

Input current switches between on and off states; under small ripple approximation, the input capacitor RMS current is approximately $I_{out}\sqrt{D(1-D)}$, which is ~0.986 A in this example. The input capacitor does not just "absorb some high-frequency noise"; it also handles significant pulsed current and thermal burden. TI: Buck Capacitor Selection

Where does the ripple factor 1/8 come from?

Capacitor-voltage extrema occur at current zero crossings, whereas ESR extrema follow current peaks. Set ESR to zero to isolate the triangle-area factor 1/8, then raise ESR and compare combined peak-to-peak ripple with the sum of individual peak-to-peak values. The latter is an upper bound.

$$\Delta V_C=\frac{\Delta I}{8fC},v_{ripple}(t)=\frac{1}{C}\int i_C(t)dt+ESR{i}_C(t)$$

Boost and Buck-Boost

When the Boost main switch is on, the inductor stores energy from the input, the diode is reverse-biased, and the output capacitor supplies current to the load; when the main switch is off, the inductor current flows through the diode to the output, and the input simultaneously participates in supplying energy. The inductor does not magically generate output power.

The ideal CCM volt-second balance is $D{V}_{in}+(1-D)(V_{in}-V_{out})=0$, yielding $V_{out}=V_{in}/(1-D)$. The real duty cycle cannot infinitely approach 1 to achieve infinite boost; on-time, parasitic losses, current, and device voltage all impose limits.

A "2 A Boost Chip" May Not Output 2 A

If boosting from 5 V to 12 V with an output of 1 A, assuming 90% efficiency, the average input current is approximately $12/(5\times 0.9)=2.667$ A, and the average inductor current is close to this value; the peak current adds ripple on top of this. If the device's "2 A" refers to the switch peak current limit, it is insufficient based on average energy alone; you cannot label the switch current limit as the load capability under any input/output condition.

After a typical non-synchronous Boost controller shuts down, the input may still be connected to the output through the inductor and diode, so there may not be true output disconnection, short-circuit isolation, or the ability to bring the output to zero. Synchronous devices also require checking specific reverse blocking and shutdown strategies. TI: Power Topologies Handbook

The traditional inverting Buck-Boost has $V_{out}/V_{in}=-D/(1-D)$ in ideal CCM, with opposite output polarity. Four-switch non-inverting Buck-Boost, SEPIC, and other structures have different connections and operating phases; this single negative sign formula does not cover all "buck-boost" types. Charge pumps also belong to a class of switching converters and do not necessarily use inductors.

Regulation Accuracy and Dynamic Response

The feedback divider ratio gives the nominal output relationship, but reference error, feedback pin current, resistor ratios, and trace voltage drops will change the actual output. Line regulation describes the effect of input changes, and load regulation describes the effect of load changes; neither is the same metric as the transient droop during a large load step.

When the load increases suddenly, the control loop and inductor current cannot change infinitely fast, so the capacitor first makes up for the current deficit. The voltage change can be estimated from $\Delta V=\int (I_{load}-I_{source})dt/C$, considering ESR and loop inductance. Increasing capacitance may improve initial droop, but it also changes poles, startup burden, and loop requirements; it is not always better to have more.

Loop bandwidth is affected by the power stage, sampling/modulation, and compensation. Topologies like CCM Boost may have a Right Half Plane (RHP) zero: increasing the duty cycle initially reduces the time for energy transfer to the output, and only later does the inductor current rise. This limits the achievable control response and you cannot directly copy Buck compensation experience. TI: Switching Power Supply Control Models

Identifying the Commutation Loop

Layout first identifies paths where current changes abruptly during switching, then looks at high-current and high dv/dt nodes. In Buck, the high di/dt commutation loop focuses on the input capacitor, high-side switch, low-side diode/switch, and their return path; inductor current is approximately continuous, so you cannot broadly treat all long paths passing through the inductor and output capacitor as the single critical loop. TI: Buck High-Frequency Loop Layout

In Boost, the switch and output rectification paths alternate commutation, so the critical loop on the output side is different from Buck. Keep the corresponding high-frequency capacitors close to the commutation devices, minimize loop inductance, and do not aimlessly expand copper area on high dv/dt switching nodes; keep feedback and sensitive signals away from these areas, while maintaining continuous and understandable return paths.

"Single-point grounding" and "solid ground plane" are not slogans that can be chosen arbitrarily without considering frequency and return paths. Connect according to the chip's PGND/AGND definitions, sampling positions, and reference layout arrangements to prevent power current voltage drops from entering the feedback reference. Thermal copper areas should also be weighed against parasitic coupling.

Faults and Startup Boundaries

For example, if a 100 μF output capacitor rises to 3.3 V within 1 ms, the average charging demand is only ~0.33 A, which needs to be added to the simultaneously operating load. Soft start can regulate the controlled process, but it may not limit all surges through diodes or other paths when plugging in.

from math import sqrt, isclose
vin, vout, current, frequency, inductance = 12, 5, 2, 500e3, 10e-6
duty = vout/vin
ripple = (vin-vout)*duty/(inductance*frequency)
cap_ripple = ripple/(8*frequency*47e-6)
esr_ripple = ripple*.02
cin_rms = current*sqrt(duty*(1-duty))
assert isclose(ripple, 7/12)
assert current-ripple/2 > 0
boost_input = 12*1/(5*.9)
assert boost_input > 2
assert isclose(100e-6*3.3/.001, .33)
print(f"Buck Peak {current+ripple/2:.3f} A, Input Capacitor RMS ~ {cin_rms:.3f} A")
print(f"Capacitor/ESR Ripple Components {cap_ripple*1000:.3f}/{esr_ripple*1000:.3f} mV")
print(f"Boost Input Average {boost_input:.3f} A; these are simplified models, not actual power supply measurements")

Quick reference for specific models should retain temperature, package, and current limit definitions corresponding to the specifications; listing only voltage, current, and frequency columns is insufficient to prove continuous operation on a specific board. The subsequent Logic Gates and Boolean Algebra enters digital circuits, but power integrity and port levels are still constrained by the analog considerations in this article.