--- title: Combinational Logic Circuits url: https://doc.liz6.com/en/hardware/05-digital-circuits/02-combinational-logic-circuits locale: en area: hardware tags: - hardware - digital-circuits date: 2026-06-30 modified: 2026-07-16 description: Combinational Logic Circuits What is Combinational Logic Combinational Logic — The output depends only on the current inputs, with no memory function. Combinati… --- # Combinational Logic Circuits ## What is Combinational Logic **Combinational Logic** — The output depends only on the current inputs, with no memory function. Combinational Logic: Output depends only on current inputs Inputs Combinational Logic Pure gate circuits · No feedback Outputs Difference from sequential logic: No clock, no state retention. --- ## Common Combinational Circuits ### Multiplexer (MUX) 2-to-1 MUX: Route A or B to output Y based on select line S A B S Select Line 2-to-1 MUX Y Y = S ? B : A (S=0 selects A, S=1 selects B) — Y = Ā·S + B·S Applications: Signal routing, parallel-to-serial conversion, logic function implementation ### Decoder ``` n-bit input → 2ⁿ-bit output (only 1 bit is high at a time) 2-to-4 Decoder: A1 A0 | Y0 Y1 Y2 Y3 0 0 | 1 0 0 0 0 1 | 0 1 0 0 1 0 | 0 0 1 0 1 1 | 0 0 0 1 Applications: Address decoding (chip select signals), 7-segment display driving Typical chips: 74HC138 (3-to-8), 74HC154 (4-to-16) ``` ### Encoder ``` Inverse of a decoder: 2ⁿ-bit input → n-bit output Priority Encoder: When multiple inputs are active simultaneously, the output encodes the highest priority input. Typical: 74HC148 (8-to-3 priority encoder) ``` ### Adder #### Half Adder (HA) Half Adder (HA): Adds two bits, outputs Sum and Carry A B Half Adder HA S = A⊕B (Sum) C = A·B (Carry) No carry input; can only perform addition for the least significant bit. #### Full Adder (FA) Full Adder (FA): Includes carry input Cin, allowing cascading A B Cin Full Adder FA S = A⊕B⊕Cin (Sum) Cout = A·B + (A⊕B)·Cin Cout = A·B + (A⊕B)·Cin — Carry out if majority of inputs are 1. Cascading n full adders creates an n-bit adder. #### Ripple Carry vs. Carry Lookahead ``` Ripple Carry: Carry propagates stage by stage → Large delay (n×t_fa) Simple, area-efficient Carry Lookahead: All carries calculated in parallel → Small delay (O(log n)) High complexity, larger area Typical: 74HC283 (4-bit carry lookahead adder) ``` ### Comparator Comparator: Bit-by-bit comparison, outputs three magnitude relationships A B Comparator A > B A = B A < B Compares bit by bit from most significant to least significant. Typical chip: 74HC85 (4-bit comparator). --- ## Programmable Logic ### Basic Concept ``` Implement any logic using programmable devices instead of building gate circuits PAL/GAL: Programmable AND array + Fixed OR array CPLD: Multiple PAL blocks + Programmable interconnect FPGA: Look-Up Table (LUT) + Flip-flops + Programmable interconnect ``` ### FPGA LUT ``` An n-input LUT can implement any n-input logic function 3-LUT: 8 SRAM cells store the truth table + 3-level MUX tree → Implements any 3-input Boolean function! Typical: 6-LUT (Xilinx), 4-LUT + Adder (Intel ALM) ``` --- ## Timing Issues ### Propagation Delay (tpd) ``` Time required for a signal to stabilize from input to output When multiple gates are cascaded: Total delay = Sum of individual gate delays Critical Path: The path with the longest delay → Determines the maximum operating frequency of the circuit ``` ### Glitches and Hazards ``` Different delays on multiple paths → Output may produce glitches Detection: Check Karnaugh maps for uncovered adjacent prime implicants Resolution: Add redundant terms or synchronize the output using a clock (registering the signal) ``` --- ## Common Applications | Circuit | Function | Chip | |------|------|------| | Tri-state Buffer | Control bus access | 74HC125/126 | | Bus Transceiver | Bidirectional data transfer | 74HC245 | | Latch | Level-triggered hold | 74HC373/573 | | Shift Register | Serial/Parallel conversion | 74HC595 | --- *Keywords: Combinational Logic, MUX, Decoder, Adder, Comparator, FPGA, LUT, glitch, Critical Path*