Sequential Logic Circuits

What is Sequential Logic

Sequential Logic — The output depends not only on the current inputs but also on the historical state.

Core Features: Clock Signal (Clock) + State Retention

Latches and Flip-Flops

SR Latch (Basic Storage Unit)

NOR Implementation:
    ┌───┐
S ──┤   ├── Q
    │NOR│
    │   ├──┐
    └───┘  │
    ┌───┐  │
R ──┤   ├──┘── Q̄
    │NOR│
    └───┘

S=1, R=0 → Set   (Q=1)
R=1, S=0 → Reset (Q=0)
S=0, R=0 → Hold  (Hold State)
S=1, R=1 → Forbidden! (Q=Q̄=0, and indeterminate upon release)

D Latch (Level-Triggered)

Level-Triggered: Follows D while CLK=1; Latches when CLK=0

D ────┬── Q
      │
CLK ──┘

Issue: If D changes while CLK=1, Q follows (Transparent Mode)
       This can cause oscillation in feedback loops.

D Flip-Flop (Edge-Triggered) — Workhorse of Digital Circuits

Symbol:
    ┌───┐
D ──┤D  Q├── Q
CLK─┤>   │
    └───┘

Samples D only on the rising clock edge (↑); Q remains unchanged otherwise.

Key Timing Parameters:
  tsu (setup): Minimum time D must be stable before the CLK edge
  th  (hold):  Minimum time D must be maintained after the CLK edge
  tcq (clk→q): Delay from CLK edge to Q update

Violating tsu/th → Metastability → Q oscillates or becomes indeterminate!

Other Flip-Flops

JK Flip-Flop:
  J=1, K=0 → Q=1  (Set)
  J=0, K=1 → Q=0  (Reset)
  J=1, K=1 → Q toggles (Toggle)
  J=0, K=0 → Hold

T Flip-Flop (Toggle):
  T=1 → Toggles on every clock edge
  T=0 → Holds state

Cascaded T Flip-Flops = Counter

Register (Register)

n D Flip-Flops sharing the same clock = n-bit Register

    ┌───┐
D0 ─┤D  Q├── Q0
    │>  │
    └───┘
    ┌───┐
D1 ─┤D  Q├── Q1
    │>  │
    └───┘
    ...   ← Total n units
    ↑
   CLK

On every rising clock edge, all D inputs are sampled → Q updates.
This is the fundamental principle behind registers and pipeline registers in CPUs.

Counter (Counter)

Asynchronous (Ripple) Counter

Q0 → CLK1 → Q1 → CLK2 → Q2 ...
The Q output of the previous stage directly drives the CLK of the next stage.

Simple but slow (cascaded delay accumulates) + Glitches occur in intermediate states.

Synchronous Counter

All flip-flops share the same clock.

Supports any counting sequence (Up/Down/Reversible).
Typical: 74HC161 (4-bit Synchronous), 74HC193 (Reversible)

Common Counting Schemes

Binary: 0→1→2→...→2ⁿ-1→0
Decimal: 0→1→...→9→0 (BCD Code)
Gray Code: Only 1 bit changes at a time (Prevents Race Conditions)
  BCD:     000→001→010→011→100...
  Gray:    000→001→011→010→110...
  Only 1 bit toggles per step → Suitable for cross-clock-domain transmission.

Finite State Machine (FSM)

Moore Machine

Mealy Machine

FSM Implementation

1. State Encoding (Binary / One-Hot / Gray)
2. Current State → Register
3. Next State → Combinational Logic (State + Input → Next State)
4. Output Logic → Moore/Mealy

One-Hot Encoding: N states = N bits, only 1 bit is '1' at a time.
  Pros: Simple output/next-state logic.
  Cons: Requires more flip-flops.

Timing Analysis

Setup and Hold Time

     tsu  th
     ├──┤├┤
D ───┘    └────────────
         ↑
CLK ─────┘    ─────────

tsu: Time D must be stable before the clock edge.
th:  Time D must be maintained after the clock edge.

Violation → Metastability!

Maximum Frequency

fmax = 1 / (tcq + tcomb(max) + tsu)

tcq:    Flip-flop CLK→Q delay.
tcomb:  Combinational logic maximum delay (Critical Path).
tsu:    Setup time of the next flip-flop.

To increase fmax:
- Reduce the number of combinational logic stages.
- Insert pipeline registers (split long paths into segments).

Metastability

When D changes within the tsu/th window:
  Q may enter an intermediate voltage level → Oscillate → Eventually settle to 0 or 1.

Mean Time Between Failures (MTBF):
  MTBF ∝ e^(t_wait/τ) / (f_clk × f_data)

Solution: Synchronizer (Double Flop)
  async_in → [DFF] → [DFF] → sync_out
             ↑CLK      ↑CLK
  
  The first stage may become metastable, but the second stage almost always resolves it.

Clock Domain Crossing (CDC)

Golden Rules for Cross-Clock-Domain Signal Transmission:

1. Single-bit signals: Use a double-flop synchronizer.
2. Multi-bit buses: Use an Asynchronous FIFO or Handshake Protocol.
   Do NOT directly synchronize multi-bit signals! (Bits may be captured in different cycles.)
3. Slow-to-Fast: Signal must remain stable for at least 2 fast clock cycles.
4. Fast-to-Slow: Signal must remain stable long enough to be sampled by the slow clock.

Keywords: Flip-Flop, DFF, Setup Time, Hold Time, Metastability, Finite State Machine, Moore, Mealy, CDC, Synchronizer