Display and Camera Interfaces

Interface Overview

HDMI (External Monitor)

Version Evolution

HDMI 1.4:  4K@30Hz, 10.2 Gbps
HDMI 2.0:  4K@60Hz, 18 Gbps, HDR
HDMI 2.1:  8K@60Hz/4K@120Hz, 48 Gbps, VRR/ALLM

Note: The HDMI 2.1 standard has deprecated the term "HDMI 2.0".
      HDMI 2.0 is now considered a subset of HDMI 2.1.
      Therefore, ask: "Does it support 48Gbps and VRR?" rather than just checking the version number.

Electrical

TMDS (HDMI 1.4/2.0): 3 data channels + 1 clock channel
FRL (HDMI 2.1): 4 data channels (Fixed Rate Link), up to 12Gbps per channel

Differential 100Ω, AC coupled
DDC (I2C over HDMI): EDID to read monitor capabilities
CEC: Consumer Electronics Control (one remote controls multiple devices)
HPD: Hot Plug Detect

DisplayPort (External/Built-in)

Versions

DP 1.2:  4K@60Hz, 21.6 Gbps
DP 1.4:  8K@60Hz (DSC compression), 32.4 Gbps, HDR
DP 2.0:  16K@60Hz (DSC), 80 Gbps (UHBR20)
DP 2.1:  Same bandwidth as 2.0, specification improvements

UHBR (Ultra High Bit Rate):
  UHBR10: 10 Gbps/lane × 4 = 40 Gbps
  UHBR13.5: 13.5 × 4 = 54 Gbps
  UHBR20: 20 × 4 = 80 Gbps

Comparison with HDMI

eDP (Embedded DP)

Laptop built-in screen interface
Based on DP protocol, with reduced power consumption and EMI
v1.4/v1.5 support 4K@120Hz internal screens
Typically 1~4 lanes

MIPI (Mobile/Embedded Mainstream)

Why MIPI

LVDS/HDMI consume too much power → Mobile/embedded devices need low-power solutions
The MIPI Alliance defines a series of interface standards for mobile devices

Two main display/camera interfaces:
  DSI (Display Serial Interface): Chip → Screen
  CSI (Camera Serial Interface): Camera → Chip

D-PHY vs C-PHY

D-PHY: Differential clock + 1~4 pairs of differential data
       Per lane: Up to ~4.5 Gbps (v2.5)
       Common: 2-lane or 4-lane

C-PHY: 3-phase encoding (3 wires transmit 2.28 bits/symbol)
       Per lane: Up to ~6 Gsps
       Fewer pins but more complex

MIPI DSI

Typical Connection:
  MPU ── DSI (2-lane or 4-lane) ──→ LCD/OLED Panel

DSI Command Mode:
  Similar to SPI, the screen has its own frame buffer
  Suitable for static/low refresh rate content

DSI Video Mode:
  Continuous screen refresh, no frame buffer
  Suitable for animations/video

Resolution Range: 480p (1-lane) ~ 4K (4-lane D-PHY v2.0+)

MIPI CSI

Typical Connection:
  Camera Sensor ── CSI (2/4 lane) ──→ ISP/MPU

Usually unidirectional (Sensor → Host)
Independent clock recovery per lane (DDR sampling)

Common Configurations:
  1080p@60fps: 2-lane
  4K@30fps: 4-lane (or 2-lane × 2)
  4K@60fps: 4-lane C-PHY or higher frequency D-PHY

CSI-2 also supports virtual channels: Multiple cameras sharing the same CSI bus

Other Display Interfaces

RGB (MCU Screen / 8080/6800 Parallel)

Legacy/Low-resolution screen interface
8/16 data lines + Read/Write, Chip Select, Command/Data Select

Parallel data → Many wires, speed limited (Fmax ~30MHz)
Used for: Small screens (< 480×320), industrial screens, low-cost products

LVDS (Marginalized)

Legacy interface for laptop internal screens, being replaced by eDP
4 pairs of differential data + 1 pair of differential clock
Typical: Single-link 1366×768, Dual-link 1920×1080

VGA (Analog, Obsolete)

R/G/B analog signals + H-Sync/V-Sync
15-pin D-Sub
Low bandwidth, signal quality degrades with cable length

Quick Selection Guide

Scenario                          Recommendation
────────────────────────────────────
External Monitor (PC/Laptop)      DP > HDMI
TV/Projector                      HDMI
Laptop Internal Screen            eDP
Mobile/Embedded Screen            MIPI DSI
Camera Module                     MIPI CSI
Raspberry Pi/ARM Dev Board        MIPI DSI/CSI or HDMI
Small/Low-Resolution              SPI/RGB (MCU Screen)

Keywords: HDMI, DisplayPort, eDP, MIPI, DSI, CSI, D-PHY, C-PHY, TMDS, DSC, EDID