Display and Camera Interfaces

“Supports 1080p60” is not enough to determine whether a screen or camera can be connected: RGB888 display transmits three color components per pixel, while Bayer RAW10 cameras typically transmit only one 10-bit sample per photosite; at the same resolution and frame rate, the data volume can vary significantly. Interface design requires checking content format, protocol, physical layer, pinout, and power sequencing separately.

Interfaces are not simply phased out by era: parallel cameras, RGB, and LVDS panels still have uses in some embedded and industrial systems. Selection should be based on device support and system constraints, rather than relying on generalizations like “DP is always better than HDMI” or “parallel interfaces are only for low resolution.”

Calculate Effective Pixels First, Then Understand Blanking and Line Coding

The starting point for effective data rate is Width × Height × Frame Rate × Bits per Pixel. For 1920×1080 at 60 Hz with RGB888, the effective area data rate is 2.985984 Gbit/s. If RGB has 10 bits per component (30 bits/pixel), it increases by 25%; YCbCr 4:2:2 and 4:2:0 reduce the average data volume by reducing chroma sampling, but this affects color detail, especially around desktop text edges.

For pixel-scanned interfaces, time must also be allocated for horizontal/vertical blanking. Assuming a teaching timing of 2200×1125 total, with a 60 Hz pixel clock of 148.5 MHz, the scan slot budget calculated at 24 bits is 3.564 Gbit/s, which is higher than the value for the effective area alone.

Traditional HDMI TMDS, in the common case of RGB888, sends one 10-bit symbol per pixel clock on each of the three data channels, totaling 148.5M×10×3=4.455 Gbit/s. During blanking, instead of sending black RGB pixels, control and data island structures are used; this calculation is used to illustrate clock and line coding budgets.

DP, DSI video mode, and CSI-2 all have packetization mechanisms, so the above TMDS calculation cannot be directly applied. What truly needs to be compared is the transmission required for the specified mode versus the available capacity after deducting coding, packet headers, and scheduling overheads from the link. DSC is used to reduce display traffic, usually designed to be visually lossless, which does not mean bit-for-bit lossless, nor does it imply that both transmitter and receiver support this compression mode. VESA: DisplayPort and DSC

HDMI: Beyond Video Data, There Is Also Capability for Reading and Control

Traditional TMDS uses three differential data channels and a separate clock channel; FRL uses a fixed link rate with embedded clock, and different modes can use three or four lanes, so not all FRL can be drawn as fixed four lanes. HDMI 2.1's capability ceiling was once raised to 48 Gbit/s, and HDMI 2.2 has expanded to a maximum of 96 Gbit/s; these are specification capabilities, not indicating that every port labeled with that version implements the maximum rate or all features. HDMI Official: 2.2 Overview

EDID tells the host what the device claims to support, but it cannot prove that the current cable and actual link have sufficient margin; converters and docks may also affect visible capabilities. Version numbers should be viewed in conjunction with explicit capabilities such as rate, color depth, HDR, VRR, DSC, and audio.

HDMI cannot be uniformly labeled as “all differential lines are AC coupled.” Traditional TMDS DC bias/termination differs from FRL or bridge chip internal interfaces; coupling and termination should be handled according to the reference design for the specific transmitter, receiver, and mode used, to avoid arbitrarily adding capacitors at both ends that would disrupt DC conditions. TI: TMDS/FRL Coupling Methods

DisplayPort and eDP: Lane Count and Rate per Lane Jointly Determine the Budget

DP Main Link transmits video and other data, AUX is used for capability reading, link management, and other controls, and HPD indicates connection and events. Link coordination between transmitter and receiver cannot be guaranteed solely by “plugging it in” to ensure the highest tier.

These budgets still need to be verified against actual stream formats, lane configurations, and implementations. Simply labeling DP 2.1 cannot replace the specific capabilities of UHBR10/13.5/20. MST can carry multiple display streams between supported devices, but they share the link bandwidth; multiple screens do not mean each screen gets a full link. eDP is aimed at embedded panels, with control and power-saving mechanisms suitable for panels, and its connectors, power, and backlight interfaces cannot be directly swapped with external DP.

USB-C DP Alt Mode commonly features two lanes for video plus USB 3.x, or four lanes for video plus an independent USB 2.0 path. Resolution/refresh rate cannot be fixed to correspond to “two lanes 4K60, four lanes 8K30,” because HBR/UHBR tiers, bit depth, and compression change the budget. USB and Type-C

MIPI: DSI/CSI-2 are Protocols, D-PHY/C-PHY are Physical Carriers

MIPI Alliance defines various interfaces, and “MIPI” cannot be treated as a unified voltage standard. DSI/DSI-2 is aimed at displays, CSI-2 at cameras; both can use related PHYs, but their data formats, controls, and connection directions differ, and they cannot be directly interconnected just because the number of differential lines is the same.

Traditional C-PHY’s 16 bit / 7 symbol encoding is approx. 2.286 bit/symbol/trio, so 1 Gsymbol/s corresponds to approx. 2.286 Gbit/s of encoded carrying capacity; symbol rate cannot be directly written as Gbit/s. Available modes and higher capabilities vary with PHY version, and the article does not replace device specifications with a fixed “max 4.5G/6G.” MIPI: D-PHY, MIPI: C-PHY Encoding Description

DSI Command Mode and Video Mode, The Difference Lies in Who Is Responsible for Maintaining the Refresh Rhythm

Command mode usually writes area data to the panel-side display memory, which is then organized for scanning internally by the panel; it is suitable for on-demand updates, but this does not mean it can only display low refresh rates or static content. In practice, DCS commands, window settings, and TE (Tearing Effect) synchronization methods are also used to reduce conflicts between writing and scanning. MIPI: DSI

Video mode provides a continuous video stream to the host according to the selected timing, which can be organized in burst/non-burst modes. Whether the panel internally has row buffers or other storage depends on the implementation, and it cannot be generalized as “video mode absolutely has no frame buffer.” When stream loss or configuration errors occur, the panel may not be able to retain the correct display itself; the host display controller, memory bandwidth, and DSI transmission must jointly satisfy the timing.

Connecting another DSI panel of the same resolution may also require completely different power-on, reset, initialization commands, lane count, pixel format, and timing. Consistent ribbon cable pin count does not mean pinout or voltage compatibility.

CSI-2: Pixel Bit Depth, Packing, and Control Links Must Be Checked Together

CSI-2 organizes image streams through packet headers containing data type, virtual channel, and length information. Virtual channels can distinguish different streams on the same physical link, but multiple cameras usually require appropriate aggregation/bridging or sensor output support, and two transmitters cannot be directly connected in parallel to the same data line. Virtual channels do not increase physical bandwidth. MIPI: CSI-2 Multi-Camera Organization

Outside the camera's data path, there are usually register control interfaces, external reference clocks, power, reset/powerdown, and other signals. The control interface can read the chip ID, which only proves that the control path is responsive; CSI-2 clock, lane mapping, settle, data type, and receive buffer may still not be configured correctly.

Bayer RAW10 has one 10-bit sample per photosite, not three 10-bit components for RGB; in traditional compact packing, four samples occupy five bytes. If the receiver expands this to a 16-bit container, the memory data volume increases, and the application must also know the stride, byte order, Bayer arrangement, and valid bit positions. Altera: RAW10 Packing and Receive Constraints

For 1920×1080 at 60 fps, the effective data rate for RAW10 is 1.24416 Gbit/s. Assuming only 20% extra budget is reserved for teaching purposes, each of the two data lanes needs approx. 0.746496 Gbit/s; this is not a unified margin in the specification, and the real value is also affected by packet overhead, line intervals, embedded data, and source high-speed transmission duty cycle. Announcing that two lanes or four lanes are mandatory based solely on “1080p60” is insufficient.

This frame of RAW10 compact data is 2.592 MB, expanding to RAW16 results in 4.1472 MB, and ISP output RGB888 is 6.2208 MB. If RAW16 is first written by DMA and then read by the ISP, and RGB is written back and then read by the display controller, this alone results in approx. 2×248.832+2×373.248=1244.16 MB/s of memory traffic, not counting other accesses. Actual pipelines may directly stream connect to reduce memory round-trips, so this is a budget for a specific architecture and cannot be used as a fixed overhead for all camera systems.

How do four 10-bit samples fit five bytes?

Change only a sample’s low pair: the first four bytes stay fixed while its field in byte five changes. Crossing a multiple of four increments the upper byte. Comparing 40 wire bits with 64 container bits separates precision from storage width.

RGB Scanning and 8080/6800 Parallel Interfaces Are Not the Same Interface

RGB scanning interfaces usually provide parallel color bits, pixel clock, and timing signals such as DE/HSYNC/VSYNC, with the host continuously sending pixels. 8080/6800-style MCU interfaces use read/write strobes, command/data selection, and data buses to access display controller registers or VRAM, with the display controller responsible for scanning. Placing both in the same set of “8/16-bit plus read/write” wiring diagrams will directly mislead hardware selection.

SPI small screens are also often updated via controller VRAM. A 480×320, RGB565 frame requires 307200 bytes; at 40 Mbit/s single-line SPI, even ignoring commands and gaps, the maximum full-frame rate is approx. 16.28 fps, while 60 fps full-frame requires 147.456 Mbit/s. Local refresh can significantly reduce data volume, but it should be calculated based on the actual changed area and controller window commands, not inferred from “small screen size” to imply smoothness.

Panel LVDS often uses specific pixel serial mapping, with the number of data pairs, single/dual link, and bit width varying by panel; differences in JEIDA/VESA mappings can cause color errors. VGA transmits analog RGB and sync, and its image quality depends on analog bandwidth, timing, and cables, and cannot be directly deduced as “analog means only low resolution.” They all require corresponding transmitter and panel/monitor specifications.

Troubleshoot Layers by Image Phenomena

Recalculate Pixel, Lane, and Memory Budgets

from math import isclose

w, h, fps = 1920, 1080, 60
assert w*h*fps*24 == 2_985_984_000
pixel_clock = 2200*1125*fps
assert pixel_clock == 148_500_000
assert pixel_clock*10*3 == 4_455_000_000
raw10_frame = w*h*10//8
raw16_frame = w*h*2
rgb_frame = w*h*3
assert (raw10_frame, raw16_frame, rgb_frame) == (2592000, 4147200, 6220800)
assert isclose(w*h*fps*10*1.2/2, 746_496_000)
assert 2*(raw16_frame+rgb_frame)*fps == 1_244_160_000
small_frame_bits = 480*320*16
assert small_frame_bits*60 == 147_456_000
assert isclose(40e6/small_frame_bits, 16.276041666666668)
print('Display scan, RAW10 lane, memory traffic, and SPI refresh budget checks passed')

These are budgets under given formats and architectures, without verifying throughput by connecting to a real monitor or camera.

Continue Reading

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• Sensors: Sampling, noise, and data quality.
• DRM and Graphics: How display state maps to kernel interfaces.