PCB Design Fundamentals

Schematics only indicate which nodes are connected; the PCB determines the resistance, inductance, capacitance, return paths, and thermal dissipation of those connections. An ideal wire in a schematic can become a source of voltage drop, reflection, or crosstalk on the board. The core of layout and routing is to ensure that real current paths satisfy electrical, thermal, mechanical, and manufacturing requirements, rather than simply connecting all nets as quickly as possible.

Stackup Determines Electromagnetic Reference First, Then Routing Rules

A four-layer board might use a structure like top signal, inner reference plane, inner power/signal, and bottom signal, but there is no single stackup that fits all projects. If high-speed traces on the bottom layer are close to a split power plane, you must check the return path; you cannot assume that every trace has an adjacent continuous reference just because another layer has a solid ground plane.

Interlayer distance, dielectric constant, copper weight, and solder mask together affect impedance and coupling. FR-4 is a material category, not a fixed dielectric constant; Tg is a glass transition-related metric, not the maximum operating temperature for long-term use. Determine the manufacturable stackup and tolerances with the PCB fabricator first, then define trace width, spacing, and impedance targets. This avoids discovering after routing that the preset geometry cannot be manufactured.

Why Return Currents Cannot Be Judged by DC Continuity Alone

Low-frequency current distribution is dominated by resistance, while high-frequency return currents tend to minimize path impedance, concentrating near the reference plane and under the signal trace. When a plane has a slot, even if a multimeter still measures continuity between two ground points, the return current may take a long detour, increasing the loop area and coupling with other circuits.

Therefore, mixed-signal layouts often isolate interference through functional partitioning and control of current paths, rather than mechanically splitting analog and digital grounds. The connection of AGND/PGND for specific ICs must be handled according to their current structure and manufacturer layout guidelines; isolation barriers, antennas, or certain magnetic components may require specific no-route zones. "Filling everything with ground" is not a universal rule. TI High-Speed Layout Guide

When signals change layers, consider the transition of the reference plane. If the signal references different planes of the same ground network before and after, provide nearby return vias at appropriate locations. If the reference switches from ground to a different power plane, the high-frequency return relationship must be analyzed separately; simply adding an unrelated ground via does not guarantee continuity.

Do two DC paths share high-frequency current equally?

By default A has lower resistance and B lower inductance. A carries most current at low frequency, B at high frequency. Raising B to 300 nH removes that advantage. The phasor diagram places B at the end of A, always ending at (1,0): magnitudes can sum above 1 A without violating KCL. A real reference plane is distributed; this two-path model isolates why sharing changes with frequency.

$$\frac{I_A}{I}=\frac{R_B+j\omega L_B}{R_A+R_B+j\omega (L_A+L_B)},I_A+I_B=I$$

Trace Width: Calculate Voltage Drop First, Then Verify Temperature Rise

The DC resistance of a rectangular copper trace is approximately R=ρL/(wt). Using room temperature copper resistivity of 1.72×10⁻⁸ Ω·m, a length of 50 mm, width of 0.5 mm, and thickness of 35 μm, the resistance is approximately 49.1 mΩ; at 2 A, the voltage drop is about 98.3 mV, and power loss is about 0.197 W. This shows that trace width issues are not just about "burning out"; they may first exceed the voltage drop budget of low-voltage power supplies.

Temperature rise also depends on adjacent copper planes, board thickness, enclosure, airflow, inner/outer layers, and other heat sources. You cannot derive a fixed temperature directly from this power dissipation, nor can you establish a rule like "inner layer current is uniformly half of the outer layer." Large copper pours for high current may also be limited by pad necking, thermal pad connections, or via bottlenecks. Check the narrowest cross-section along the entire path.

Via resistance and inductance vary with hole diameter, copper plating thickness, length, and return structure; they are not fixed at 1 A or 1 nH per via. Multiple vias can distribute current and heat, but actual current sharing is influenced by geometry. Hot spots, connectors, and solder joints must also be included in verification.

High-Speed Routing: Handle by Propagation Time and Interface Budgets

Whether a digital signal requires transmission line treatment depends mainly on edge rates and interconnect delay, not just clock frequency. Assuming an effective dielectric constant of 3, the propagation speed is approximately c/√3. A one-way delay of 100 mm is about 0.578 ns; for edge rates in the 1 ns range, this interconnect cannot be easily treated as an ideal wire. Actual field distribution, structure, and losses require appropriate models.

Differential impedance is determined jointly by the reference relationship of each single trace and the coupling between the two traces. Tighter spacing is not necessarily better. Use field solvers or geometry rules confirmed by the PCB fabricator based on interface targets and actual stackup. Before using an empirical formula, check its assumptions about microstrip, stripline and reference-plane geometry.

If the design specifies a differential intra-pair propagation skew budget of 20 ps, the corresponding length difference at the above propagation speed is approximately 3.46 mm. This only demonstrates "time converted to length" and is not an allowable value for any USB, HDMI, or LVDS. Actual budgets also include package, connector, via, and receiver requirements; they cannot be uniformly written as ±5 mil.

Excessive serpentine compensation introduces self-coupling; adding geometric length does not precisely add an equivalent electrical delay. Layer changes, splits, and via stubs also change impedance and reflection. The focus is on the complete channel meeting requirements, not zero vias or visually absolute length matching.

Decoupling is an Impedance Network, Not "More Capacitance is Better"

Assuming an allowable voltage ripple of 50 mV and a load current change of 1 A, the target impedance magnitude is ΔV/ΔI = 50 mΩ. If a capacitor alone handles 1 A for 1 μs at a certain stage, the ideal capacitance required is at least C = IΔt/ΔV = 20 μF. However, effective capacitance derating under bias, ESR, and L·di/dt will continue to consume the voltage budget; this value is not the complete selection result.

Capacitors must form a short, low-inductance loop with the IC power and return. Both terminals and vias must be considered. Some back-side layouts may achieve better connections through short vias; do not judge "IC first, then via, then capacitor" as incorrect. Self-resonance and mutual connection of large and small capacitors can also form anti-resonance peaks; placing several different capacitance values does not necessarily cover all frequencies. ADI: Decoupling and Connection Inductance

For switching power supplies, first identify the commutation loops with rapidly changing current. Arrange input capacitors, switching devices, and returns according to the topology and reference layout. Switch node copper area, thermal requirements, and EMI need trade-offs. Keep feedback and sampling lines away from large current voltage drops and switching coupling. Do not treat "spreading out high-power components" as a principle prioritized over critical loops. ADI: Power Layout and EMI

Clearance: Manufacturability and Insulation Are Two Separate Requirements

Trace spacing is primarily affected by manufacturing capabilities, but electrical clearance and creepage distances involve different paths: the former through air, the latter along the insulating surface. Applicable values vary based on operating/transient voltage, basic or reinforced insulation, pollution degree, material group, altitude, and product standards. You cannot write "220 V is uniformly 2.5 mm" as a design conclusion. Solder mask cannot be assumed to satisfy required insulation without verifying conditions. TI: Clearance and Creepage

Implement the corresponding conditions into net classes and rules, then check paths between copper, pads, vias, board edges, and mechanical parts. Whether slots are effective and how to calculate distances still need to be handled according to the rules used; drawing a slot does not allow arbitrarily reducing other distances.

Layout Serves Connection, Thermal Dissipation, and Testability Simultaneously

First fix connectors, mounting holes, switches, and form factor constraints, then place critical power/analog/clock loops, with other components arranged around real connection relationships; core ICs do not necessarily need to be centered. Crystals and load capacitors should be placed according to oscillator reference layouts to minimize parasitics; do not just pursue geometric length matching for two wires.

Reserve test points for power, reset, download, and critical states that are suitable for probing. High-speed network test points may also form stubs; choose appropriate structures. Maintenance convenience cannot come at the cost of adding long stubs to every high-speed line. Antenna no-route zones for wireless modules should cover corresponding layers and mechanical space according to specific module requirements; not all external antenna areas require uniform copper clearance.

From Design Checks to Manufacturing Delivery

ERC checks schematic rules, and DRC checks configured board-level rules; neither proves correct device orientation, power strategy, or signal integrity. You must verify symbol-to-footprint pin mapping, polarity, mating direction, pad size, mechanical interference, and production processes. For critical interfaces, check actual reference planes and return paths to avoid relying solely on unconnected net counts reaching zero.

File extensions are not the only standard for semantic meaning; .GKO cannot be broadly equated to being both a keep-out layer and a board outline. Taking KiCad as an example, the board outline is defined by Edge.Cuts; manufacturing outputs can also carry layer stackup and job information. After exporting, use an independent viewer to check the final files, rather than just checking the editor view. KiCad PCB Documentation

Recalculate Board-Level Budgets

from math import sqrt, isclose
rho, length, width, thickness = 1.72e-8, 0.05, 0.0005, 35e-6
r = rho*length/(width*thickness)
assert 0.0491 < r < 0.0492
assert 0.0982 < 2*r < 0.0983
assert 0.1965 < 4*r < 0.1966
speed = 299792458/sqrt(3)
assert 0.577 < 0.1/speed*1e9 < 0.579
assert 3.46 < speed*20e-12*1000 < 3.47
assert isclose(0.05/1, 0.05)
assert isclose(1*1e-6/0.05, 20e-6)
print('Copper trace voltage drop loss, propagation delay, skew conversion, and PDN budget passed')

These calculations do not replace thermal simulation, impedance solving, applicable insulation rules, or physical board verification; no PCB was generated or put into production in this instance.

Continue Reading

• Measurement Instruments and Tools: Probe loading and waveform verification.
• Debug and Programming Interfaces: Recovery and test connections.