--- title: PCB Design Fundamentals url: https://doc.liz6.com/en/hardware/10-practices-and-tools/02-pcb-design-fundamentals locale: en area: hardware tags: - hardware - practices-and-tools date: 2026-06-30 modified: 2026-07-16 description: PCB Design Fundamentals What is a PCB? PCB (Printed Circuit Board) — A carrier that connects electronic components via copper traces on an insulating substrate.… --- # PCB Design Fundamentals ## What is a PCB? **PCB (Printed Circuit Board)** — A carrier that connects electronic components via copper traces on an insulating substrate. --- ## PCB Stackup ### Common Layer Count Choices ``` 2 Layers: Simple circuits (Arduino shield level) Top: Signals + Components Bottom: GND pour + few traces 4 Layers: Standard industrial board ★ Best cost-performance ratio Top: Signals + Components L2: GND (Solid ground plane!) L3: Vcc (Power plane) Bottom: Signals + Components 6+ Layers: High-speed / High-density boards (DDR, FPGA, Mobile Phone Mainboards) ``` ### Why a Solid Ground Plane is Necessary ``` 1. Each signal has a nearby return path → Small loop → Low EMI 2. Controlled characteristic impedance (microstrip/stripline) 3. Low-impedance path for the Power Distribution Network (PDN) 4. Inter-layer capacitance (GND-Vcc planes form natural decoupling capacitors) ``` --- ## Routing ### Trace Width and Current Carrying Capacity ``` Rule of Thumb (1oz copper, outer layer): 10mil (0.254mm) → ~1A (10°C temperature rise) 20mil → ~2A 50mil → ~4A 100mil → ~8A Use copper pours instead of traces for high current. Inner layer current capacity ≈ Half of the outer layer. ``` ### Clearance ``` Low Voltage (<50V): 6~8mil is sufficient. Mains Voltage (220V): At least 2.5mm (creepage distance). Differential Pairs: Tight and constant spacing (e.g., 5mil). ``` ### Differential Pair Routing ``` USB, HDMI, LVDS, Ethernet... Rules: 1. Equal length for both traces (length matching ±5mil) 2. Equal spacing (constant gap) 3. Route on the same layer 4. Minimize vias 5. Reference a continuous ground plane ``` ### Impedance Control ``` High-speed signals require controlled characteristic impedance: Microstrip (Outer Layer): Z₀ ≈ 87/√(εr+1.41) × ln(5.98H/(0.8W+T)) H: Distance from trace to reference plane W: Trace width T: Copper thickness Common Standards: USB 90Ω differential, 50Ω single-ended HDMI 100Ω differential SDI 75Ω single-ended Specify impedance requirements to the PCB manufacturer → They adjust trace width. ``` --- ## Vias ``` Through-hole: Passes through all layers — Cheapest Blind: Outer layer to inner layer — Expensive Buried: Inner layer to inner layer — Very Expensive Via Current Capacity: Typically <1A Use multiple vias in parallel for high current. Via Parasitics: Parasitic Inductance ≈ 1nH Parasitic Capacitance ≈ 0.5pF Minimize vias for high-speed signals. ``` --- ## Component Placement ### Basic Principles ``` 1. Place fixed-position components first (connectors, switches, LEDs) 2. Center the core ICs 3. Place decoupling capacitors as close to the IC power pins as possible (the closer, the better!) 4. Place crystal oscillators close to the IC (keep traces short) 5. Spread out high-power components; keep heat sources away from temperature-sensitive components 6. Separate analog and digital areas ``` ### Decoupling Capacitor Placement ``` IC ┌────────┐ │ VDD │ │ │ GND ← ──┤│──────┤├── ← Shortest loop from VDD to capacitor to GND! │ 0.1μF │ │ │ │ VSS │ └────────┘ Placement Order: IC Pin → Capacitor → Via to Ground Plane Avoid: IC → Via → Capacitor (Loop is too large) ``` ### Crystal Oscillator Placement ``` ┌─────┐ │ MCU │ │ Xin Xout │ │ │ │ │ │ │ ┌┴┐ │ │ └──┤C├─┘ │ ┌┴┐ │ │C│ └────┘┬┘ GND Place crystal oscillator close to IC, with equal-length symmetric traces. Pour ground under the crystal (do not route traces underneath). Load capacitors connect between crystal and GND. ``` --- ## Power Distribution ### Star vs. Plane ``` Star: Power splits from one point → Supplies each branch individually Suitable for: Separating analog and digital supplies Plane: The entire layer is the power plane Suitable for: High-speed digital circuits (low impedance) Hybrid: One solid ground plane + Split power planes Analog and digital power separated, connected at a single point ``` ### Decoupling Capacitor Network ``` Large Capacitors (10μF~100μF Electrolytic/Tantalum): Handle low-frequency transients, placed at power entry points. Small Capacitors (0.1μF Ceramic MLCC): One for each IC power pin! Place next to the pin (the closer, the better). Very High-Frequency Capacitors (1nF~10nF): May be needed for very large ICs (FPGA/CPU). Principle: Different capacitance values handle noise at different frequencies. Large capacitors → Low frequency, Small capacitors → High frequency. ``` --- ## Silkscreen and Documentation ``` Silkscreen: - Component Designators (R1, C5, U3) - Connector Function Labels - Polarity Markings (Diodes, Electrolytic Capacitors +) - Test Point Markers - Board Name / Version Number Fiducial Marks: Bare copper dots without solder mask → Used for SMT machine auto-alignment. Place 2-3 at board corners (mandatory for panelization). ``` --- ## Gerber Files ``` Standard format sent to the PCB manufacturer: Required Files: *.GTL — Top Copper *.GBL — Bottom Copper *.GTS — Top Solder Mask *.GBS — Bottom Solder Mask *.GTO — Top Silkscreen *.GBO — Bottom Silkscreen *.GKO — Board Outline (Keep-out / Outline) *.TXT — Drill File (NC Drill) Pre-production Check: Preview using an online Gerber Viewer. ``` --- ## Quick Checklist ``` □ DRC Passed (clearance, trace width, vias) □ Decoupling capacitors present for every IC □ Crystal oscillator close to IC, short traces □ Connector orientation correct (Pin 1 marking) □ Polarized components oriented correctly □ Silkscreen does not cover pads □ Test points placed □ Board outline closed □ Mounting hole dimensions correct □ High-current path trace width sufficient □ No copper pour in antenna area (for wireless modules) ``` --- *Keywords: PCB, Stackup, Routing, Impedance, Via, Decoupling, Placement, Gerber, Differential Pair*