MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)

A MOSFET may have a threshold voltage ($V_{th}$) specified as 1 V, yet still heat up when driven by a 3.3 V GPIO; the gate draws almost no DC current, but the driver may need ampere-level transient current during fast switching. These two facts are not contradictory: the threshold describes a weak-conduction test point, while gate charge describes the dynamic burden during switching. This article first clarifies the channel, operating regions, and terminals, then combines drive and loss calculations.

Four-Terminal Structure and Types

Using a planar enhancement-mode NMOS as a teaching model: there are two $n^{+}$ regions in the P-type body, forming source and drain contacts; the gate is separated from the semiconductor surface by an insulating dielectric. A positive gate-to-source voltage ($V_{GS}$) reduces surface holes and, with sufficient bias, forms an electron inversion layer, increasing conductivity between the source and drain.

The gate, source, drain, and body correspond to the four terminals G, S, D, and B. The body connection in integrated circuits affects threshold and parasitic junctions; discrete power NMOS often connects the body to the source internally and may use a vertical structure, so this planar diagram should not be taken as the actual cross-section for all power devices.

Even when $V_{GS}$ is below the threshold, there may still be an electric field and subthreshold conduction under the gate; it is not "no electric field." The threshold marks a conventional state or test current point, not an absolute cutoff between zero current and full conduction.

All of the above are subject to specific rated limits. For NMOS with the common direction $V_{DS}>0$, the convention is that drain current flows from D to S, and electrons mainly from S to D; PMOS voltage and current signs must be handled accordingly. Do not apply a unsigned "$V_{th}$ magnitude" to all conditions.

Operating Regions and Square-Law Boundary

For a long-channel, strong-inversion, gradual-channel, and approximately constant-mobility NMOS model, define $k={\mu }_n{C}_{ox}(W/L)$ and overdrive voltage $V_{ov}=V_{GS}-V_{th}$. Ignoring channel-length modulation:

In the Ohmic region, when $V_{DS}$ is small enough, the quadratic term can be ignored, and the device approximates a resistor controlled by gate voltage. As $V_{DS}$ increases, the local gate-to-channel overdrive at the drain end decreases, creating a pinch-off region; current can still flow into the drain through the high-field region, and pinch-off does not completely cut off the current.

In this ideal model, the saturation region is insensitive to $V_{DS}$ but has a square-law relationship with $V_{ov}$, meaning $I_D$ is not proportional to $V_{ov}$. Taking $k=1{\text{ mA/V}}^2$ and $V_{ov}=2\text{ V}$, when $V_{DS}=0.5\text{ V}$, $I_D=0.875\text{ mA}$; after $V_{DS}\ge 2\text{ V}$, the ideal saturation current is $2\text{ mA}$; when $V_{ov}$ increases to $4\text{ V}$, it becomes $8\text{ mA}$. This is an analytical model example, not a universal fit for power devices.

Short-channel effects, velocity saturation, mobility degradation, channel-length modulation, and the drift region in power devices all alter these relationships. Actual saturation current is not strictly horizontal, and $g_m=2I_D/V_{ov}$ only holds under the corresponding square-law conditions.

"Saturation" and "Linear Mode" Require Context

BJT saturation is often used for low-voltage-drop switch conduction; when a MOSFET is fully turned on as a low-loss switch, it is usually desired to be in the Ohmic region at low $V_{DS}$. The "saturation" of the two is not the same goal.

The "linear mode" mentioned in power documents often refers to the device acting as a controllable dissipative element, sustaining both significant voltage and current, which may correspond to the MOSFET saturation region in textbooks. For example, thermal-surge current limiting cannot simply estimate the entire startup loss using "Ohmic region on-resistance." Infineon: MOSFET Linear Operation and SOA

Why does pinch-off not stop current?

The vertical line marks VDS=Vov. Current and slope remain continuous across it; the flat tail follows the omission of channel-length modulation. Low-loss switching usually concerns small VDS on the left, not a BJT-style saturation analogy.

Reading the Datasheet: Threshold is Not a Drive Guarantee

$V_{GS(th)}$ is often measured at a very small specified drain current, whereas the application may require passing several amperes. To determine if a 3.3 V drive is suitable, look for $R_{DS(on)}$ or conduction specifications guaranteed at the actual achievable $V_{GS}$, and consider temperature and voltage drops, rather than just confirming that 3.3 V is greater than the threshold.

Common small-signal capacitances are defined as $C_{iss}=C_{GS}+C_{GD}$, $C_{oss}=C_{DS}+C_{GD}$, $C_{rss}=C_{GD}$. The charge required for large voltage transitions should be integrated along the voltage change; you cannot always use $C_{iss}\times V_{GS}$ at a single point to replace $Q_g$. Nexperia: Power MOSFET Datasheet Parameters

Bidirectional Current and Unidirectional Blocking

For common discrete NMOS with internal body-source shorting, the body and drain form a parasitic diode: anode at S/body, cathode at D. It is not "a body diode between Body and Source," because these two terminals are already connected in this structure. The PMOS body diode direction is reversed.

When the gate is off, this diode may still allow current to flow from S to D. Once the channel is fully turned on, within the applicable bias range, the channel can conduct bidirectionally, and reverse current does not necessarily all flow through the body diode. To achieve bidirectional blocking when off, two MOSFETs are often used in reverse series, with correct drive and body diode orientation.

The body diode also has its own voltage drop, recovery charge, thermal limits, and commutation conditions; do not assume it can infinitely handle freewheeling. For high-side NMOS, the source potential rises with the load node, and the gate must maintain the required drive voltage relative to the source; pulling the gate to 5 V relative to ground does not maintain a 5 V $V_{GS}$ when the source is already near 5 V.

Bootstrap high-side drivers require satisfying their charging and refreshing conditions and may not maintain 100% duty cycle continuously; charge pump or isolated supply drivers have different capability boundaries. Transient voltage drops on the source common inductance also change the $V_{GS}$ seen inside the chip.

Gate Drive Example: Low Average Current Does Not Mean Low Peak Current

The gate insulation means stable DC leakage is usually small, but each switching event requires moving charge. If at a certain operating point $Q_g=20\text{ nC}$, drive amplitude is 5 V, and frequency is 200 kHz, the average supply current for a simple resistive charge/discharge drive is approximately $Q_{g}f=4\text{ mA}$, and the drive-related energy power is approximately $Q_g{V}_{drive}f=20\text{ mW}$. This power is distributed across the driver and gate resistor paths, and cannot all be counted as internal heat loss in the MOSFET chip.

If you want to move 20 nC in about 50 ns, the average switching current given by total charge divided by time is 0.4 A. The Miller region needs separate analysis: assuming $Q_{gd}=6\text{ nC}$, if the available gate current during this stage is about 0.2 A, the duration is about 30 ns. The peak current on the driver's datasheet does not guarantee that the same current can be provided during the plateau; the actual value is determined by the drive voltage, plateau voltage, and total loop impedance. TI: High-Speed MOSFET Gate Drive

The Miller plateau corresponds to the stage where charge change couples with drain voltage transition. The plateau height varies with load current, device, and drive conditions; it is not another fixed threshold. Rapid $dv/dt$ at the drain can also couple to the off-state gate via $C_{GD}$, causing false turn-on; turn-off pull-down capability, loop inductance, and Miller clamping when needed should all be analyzed in conjunction with the circuit.

Series gate resistors are used to adjust charge/discharge speed and damping, but do not automatically "eliminate oscillation." Increasing resistance may reduce edge speed and EMI, but increases switching overlap loss. Another gate-to-source pull-down resistor is used to establish a default off state when the drive is high-impedance; its role is different from the series gate resistor.

Where does charge go during the plateau?

At the default 0.2 A, the plateau spans 40–70 ns: blue stays flat while gold falls. Increasing gate current compresses time without reducing the model’s Qgd. Real gate current also depends on plateau voltage and loop impedance.

$$t_{Miller}\approx \frac{Q_{gd}}{I_g}$$

Losses and Operating Range

When fully turned on, resistive loss is approximately $P_{cond}=I_{rms}^2{R}_{DS(on),T}$. Here, $I_{rms}$ should be calculated based on the device's conduction waveform and period; if using only a constant 5 A during conduction with duty cycle $D$, the average loss over the full period is $D\cdot 25R$.

Example: At operating temperature, $R_{DS(on)}=30\text{ m}\Omega$, and the full-cycle RMS current is 5 A, so conduction loss is about 0.75 W. If there are additional hard-switching conditions with $V=12\text{ V}$, $I=5\text{ A}$, total voltage-current overlap transition time of 50 ns, and frequency 100 kHz, a common simplified triangular overlap estimate gives $P_{sw}\approx \frac{1}{2}VI(t_r+t_f)f=0.15\text{ W}$.

This model ignores actual commutation shapes, $C_{oss}$ energy, body diode recovery, dead time, and drive variations, so it cannot be called an exact measurement of total switching loss. Its purpose is to illustrate that reducing $R_{DS(on)}$ does not guarantee a decrease in total loss: a larger chip may require more drive charge, and different generations of devices may alter this trade-off.

SOA (Safe Operating Area) describes the allowed voltage-current combinations given time and thermal conditions. During current limiting, soft-start, and short-circuit events, both significant $V_{DS}$ and $I_D$ may occur simultaneously; do not just check if each is below its individual rating. Thermal steady-state can be roughly estimated using thermal resistance under applicable installation conditions; for short pulses, look at transient thermal resistance and SOA; positive temperature coefficient helps current sharing in some fully-on parallel conditions, but does not guarantee no local thermal instability under all biases.

from math import isclose
k, overdrive = .001, 2
linear = k*(overdrive*.5-.5**2/2)
saturation = k*overdrive**2/2
assert isclose(linear, .000875)
assert isclose(saturation, .002)
qg, frequency, drive = 20e-9, 200e3, 5
assert isclose(qg*frequency, .004)
assert isclose(qg*frequency*drive, .02)
assert isclose(6e-9/.2, 30e-9)
conduction = 5**2*.03
switching = .5*12*5*50e-9*100e3
assert isclose(conduction, .75) and isclose(switching, .15)
print("Long-channel example: 0.875/2 mA; Drive estimate: 4 mA, 20 mW, Miller stage 30 ns")
print(f"Conduction loss {conduction:.2f} W, Simplified overlap loss {switching:.2f} W")

From principles to selection, one should sequentially determine the actual $V_{GS}$, conduction and commutation waveforms, temperature, and fault operating range, and then compare against guaranteed parameters and models. The next article Power Device Overview extends these conditions to IGBT, SiC, GaN, and other devices, judging "faster" or "more energy-efficient" not by a single material name.