Operational Amplifier (Op-Amp)

The "voltage equality" between the inverting and non-inverting terminals is not a hard-wired property of the op-amp itself, but an approximation resulting from high gain, stable negative feedback, and linear operation. Once the input range, output headroom, or dynamic capabilities are insufficient, continuing to use the virtual short concept will yield impossible results. This article first presents the conditions for using this approximation, then derives common circuits from node current equations.

Conditions for the Two Approximations

Voltage-feedback op-amps can describe behavior under certain linear conditions using the high-gain differential relationship $v_{out}\approx A_{OL}(v_{+}-v_{-})$. The ideal model assumes zero input current and infinite open-loop gain, but real devices have bias currents, offset, finite bandwidth, and output limitations.

"Virtual open" implies that ideal input terminals do not draw current; it does not mean there is no current at the inverting node: current still flows through the input resistor, feedback resistor, and parasitic capacitance. "Virtual short" implies that when stable negative feedback is present and the op-amp is not operating outside its range, the voltage difference between the two inputs is very small; it does not mean the two terminals are physically shorted.

If the output is saturated near the supply rails, or if the input common-mode voltage exceeds the specified range, connecting feedback to the inverting terminal does not guarantee a virtual short. If the loop is unstable, the existence of a static algebraic solution does not guarantee that the circuit will settle at that point. The positive feedback in comparators and open-loop comparison applications cannot be solved using the virtual short concept; ordinary op-amps may also not be suitable for use as comparators.

Inverting, Non-Inverting, and Follower

Inverting: Use Node Currents Instead of Memorizing the Negative Sign

The input is connected to the inverting terminal via $R_{in}$, and $R_f$ feeds back from the output to this node, while the non-inverting terminal is connected to $V_{ref}$. Assuming $v_{-}=V_{ref}$ and zero input current, the node equation is:

$(V_{in}-V_{ref})/R_{in}+(V_{out}-V_{ref})/R_f=0$,

so $V_{out}=V_{ref}-(R_f/R_{in})(V_{in}-V_{ref})$. It simplifies to $-(R_f/R_{in})V_{in}$ only when $V_{ref}=0$.

In the diagram, $V_{ref}=2.5\text{ V}$, $R_{in}=10\text{ k}\Omega$, and $R_f=100\text{ k}\Omega$. When $V_{in}=2.6\text{ V}$, the output is $1.5\text{ V}$; the input is $0.1\text{ V}$ above the reference, and the output is $1\text{ V}$ below the reference. The input branch current of $10\text{ muA}$ is balanced by the feedback network, not by flowing into the chip through the ideal op-amp input terminal.

Assuming the actual load output range is $0.2\text{–}4.8\text{ V}$, the usable input range derived from this equation is approximately $2.27\text{–}2.73\text{ V}$, and other device input common-mode and other conditions must be verified. In a single-supply circuit, you cannot ground the non-inverting terminal and still expect a positive input to produce a negative output without providing a negative supply.

Looking into this inverting stage from the signal source, the input impedance in the frequency band where the approximation is valid is primarily $R_{in}$, not the extremely high input impedance of the op-amp chip. Source series impedance also participates in the actual gain, and the loading effect of the preceding stage cannot be ignored.

Non-Inverting: Output Voltage Divider Follows Input

The non-inverting terminal is connected to the input, and the inverting terminal is connected to a voltage divider formed by $R_f$ from the output and $R_g$ to $V_{ref}$. Writing the equation for the inverting node and applying the virtual short yields $V_{out}=(1+R_f/R_g)V_{in}-(R_f/R_g)V_{ref}$.

When $V_{ref}=0$, the signal gain is $1+R_f/R_g$; the input terminal mainly handles bias and dynamic capacitive currents, but the actual input range is still constrained by the device. $R_g$ is not a resistor in series with the input signal; the circuit connection should not be drawn as the input being grounded simultaneously.

The follower connects the output directly to the inverting terminal, with the non-inverting terminal connected to the input, targeting a gain of 1. The device must support unity-gain stability, and the input common-mode, output swing, and load current must all allow for this voltage. A follower can buffer high-impedance sources, but it is not a power source for arbitrary currents; directly driving a large capacitive load may also affect stability.

Does the virtual short survive clipping?

At the default linear operating point, more open-loop gain drives the differential voltage toward zero. At Vin=3 V the lower output limit prevents tracking even at larger gain. Input-branch current still balances feedback current without entering the ideal input.

Differential and Integrator: Formulas Require Ratios and DC Paths

Four-Resistor Differential Stage

Define $R_1$ from $V_1$ to the inverting terminal, and $R_2$ from the output feeding back to the inverting terminal; $R_3$ from $V_2$ to the non-inverting terminal, and $R_4$ from the non-inverting terminal to $V_{ref}$. If $R_2/R_1=R_4/R_3=G$, the ideal equation is $V_{out}=G(V_2-V_1)+V_{ref}$.

What is required is matching of the two ratios, not forcing all corresponding resistors to be absolutely equal. Ratio errors will convert common-mode voltage into output error, and source impedance mismatch will also change the effective ratio; the op-amp's own high CMRR cannot eliminate mismatch in the external resistor network. When differential signals are small and common-mode voltages are large, instrumentation amplifiers or matched networks may be more suitable, but the entire common-mode and output operating range must still be checked.

Integrators Must Handle DC Errors

Replace the feedback resistor of the inverting stage with $C$, keep the input passing through $R$, and connect the non-inverting terminal to a constant $V_{ref}$. Using $V_{ref}$ as the signal reference, the ideal integration equation includes an initial value:

$v_{out}(t)=v_{out}(t_0)-[1/(RC)]{\int }_{t_0}^t(v_{in}-V_{ref})dt$.

Without a DC feedback path, small DC inputs, offset, or bias currents will continuously charge the capacitor, eventually pushing the output to saturation. Practical integrators can place a large resistor in parallel with the feedback capacitor to provide finite DC gain, or design reset and controlled initial values; thereafter, it approximates integration only within the applicable frequency band and can no longer claim to satisfy the ideal equation from DC to infinite frequency.

For example, with $R=100\text{ k}\Omega$ and $C=100\text{ nF}$, a constant differential input of $1\text{ mV}$ corresponds to an output slope of $-0.1\text{ V/s}$. This small input error, if sustained for several seconds, can consume a significant amount of output headroom. Capacitor leakage, dielectric absorption, and bias currents also need to be considered for precision integration applications.

How Non-Ideal Quantities Enter the Output

Signal Gain and Noise Gain Are Different

Zeroing the input signal source, the gain from the op-amp's own equivalent input voltage error to the output is called the noise gain. For a simple inverting resistor stage, the signal gain is $-R_f/R_{in}$, but the noise gain is $NG=1+R_f/R_{in}$. For a non-inverting stage, the signal gain and noise gain are the same in this simple structure. Analog Devices: Noise Gain

The inverting gain of $-10$ in the diagram corresponds to $NG=11$. If the input offset voltage is $100\text{ muV}$, this single term causes an approximate output error of $1.1\text{ mV}$, not $1\text{ mV}$. Actual errors will also stack with feedback resistor ratios, $V_{ref}$, and other sources; for uncorrelated random noise and deterministic worst-case errors, appropriate synthesis methods should be used.

Input bias currents flowing through source/feedback impedances also create offsets. For certain input structures, making the DC resistance seen by both terminals similar helps reduce the effect of matched bias currents, but it does not eliminate input offset current, and may also increase resistor thermal noise. Adding "$R_{in}\parallel R_f$" to the non-inverting terminal should not be treated as a mandatory step applicable to all input stages.

Bandwidth Approximation is Calculated Based on Noise Gain

For voltage-feedback op-amps with an approximate single dominant pole, the closed-loop small-signal bandwidth can often be estimated as $GBW/NG$. If $GBW=1\text{ MHz}$ and the inverting signal gain is $-10$, the result is approximately $90.9\text{ kHz}$, not directly calculated as $100\text{ kHz}$ based on the magnitude of the signal gain. Frequency-dependent feedback networks require looking at the crossover and phase of the noise gain curve and the open-loop response. Analog Devices: Gain-Bandwidth Relationship

$GBW$ is not a strictly constant product for all op-amps at all frequencies. Current-feedback structures, de-compensated op-amps, and multi-pole behaviors have different limitations; some op-amps require a minimum stable noise gain and cannot be directly configured as followers.

From Formulas to Practical Connections

Check Input Range, Output Range, and Supply Range Separately

Supply voltage, input common-mode range, and loaded output swing are different specifications. "Rail-to-rail input" and "rail-to-rail output" describe different ports separately; RRIO does not guarantee that the output reaches both supply rails precisely under all loads. The absolute maximum voltage allowed by input protection is not equal to the common-mode range for normal linear operation. TI: Rail-to-Rail Port Boundaries

$V_{ref}$ is a real node with impedance and noise. Dividing the supply voltage in half using two resistors does not automatically create a "virtual ground" capable of handling arbitrary signals or load currents; buffering must be decided based on the connected current, bandwidth, and error. The circuit also does not always need $V_{CC}/2$; the bias position should be determined jointly by the available input and output ranges.

Distinguish Peak and Peak-to-Peak for Slew Rate

The maximum slope of a sine wave output is $2\pi f{V}_{peak}$. If a hypothetical device has $SR=0.5\text{ V/mus}$, the peak limit derived from the slope at $20\text{ kHz}$ is approximately $3.98\text{ V}$, corresponding to a peak-to-peak value of approximately $7.96\text{ V}$; do not mistakenly label $3.98\text{ V}$ as $4\text{ Vpp}$.

This is only a slope boundary; a $5\text{ V}$ single supply often hits output headroom limits first, and satisfying the slope condition does not mean a certain THD specification has been met. Small-signal response, output amplitude, load, and distortion specifications should be viewed together.

Stability, Unused Channels, and Power-On State

Capacitive loads and output impedance can introduce additional poles; isolation resistors or compensation networks can sometimes improve stability, but they also change output error and frequency response. Do not unconditionally parallel a feedback capacitor just because ringing is observed; first confirm the loop and device recommended conditions.

Unused channels need a defined and legal input state. For devices that support unity-gain stability, a common practice is to configure them as followers and bias the non-inverting terminal within the allowed input/output range; do not leave both inputs floating, nor unconditionally connect the follower input to ground in a single-supply configuration. De-compensated devices must meet their stability gain requirements. TI: Connecting Unused Op-Amps

Power supply decoupling, current loops, and feedback node layout also affect behavior. Component values and placement are determined by the device application notes and system bandwidth; you cannot prove the design is complete just by saying "place a $0.1\text{ muF}$ capacitor on each power pin." Power-on sequence, inputs appearing before supply, and outputs being driven externally also require checking allowed conditions.

How to Filter by Task

CMOS, JFET, bipolar inputs, and chopper-stabilized technologies each have trade-offs; model suffixes, generations, and temperature grades may also change parameters. When comparing, use guaranteed values and curves under the same conditions, and do not use a "typical parameters table" without load, supply, and test conditions as the final basis.

from math import pi, isclose
rin, rf, ref, vin = 10000, 100000, 2.5, 2.6
out = ref-rf/rin*(vin-ref)
assert isclose(out, 1.5)
assert isclose((vin-ref)/rin+(out-ref)/rf, 0, abs_tol=1e-15)
noise_gain = 1+rf/rin
assert noise_gain == 11
bandwidth = 1e6/noise_gain
error = 100e-6*noise_gain
peak = .5e6/(2*pi*20000)
assert isclose(error, .0011)
assert 3.97 < peak < 3.99
assert isclose(.001/(100000*100e-9), .1)
print(f"Output {out:.2f} V, Noise Gain {noise_gain:.0f}, Single-Pole Bandwidth approx {bandwidth/1000:.2f} kHz")
print(f"Offset Contribution {error*1000:.2f} mV; SR Boundary {peak:.3f} Vpeak / {2*peak:.3f} Vpp")

The next article Power Supply Circuits will apply feedback and device capabilities to voltage regulation and energy conversion, and continue to distinguish between ideal relationships and dynamic operating conditions.

From feedback circuits to dynamic analysis

Static closed-loop gain alone does not determine oscillation. Use dynamic modeling to separate inputs, states, and outputs, then frequency response and margins for loop gain, phase, and delay. Apply the actual op-amp, load, and operating-point parameters when returning to the circuit; the thermal example supplies a method, not electronic component values.