Logic Levels and Interface Physical Layers

MCUs and peripherals may both be labeled "serial port," yet connecting them does not guarantee communication: one end might be a 3.3 V UART pin, while the other is an RS-232 interface with positive and negative voltages. Even if both ends are 3.3 V, differences in output current, input thresholds, capacitive tolerance, and trace reflections can still cause issues. Interface connections require distinguishing between the protocol being transmitted, the electrical layer used, and what each pin is allowed to do under various power states.

High and Low Levels Are Conditional Guarantees

VOH,min is the guaranteed minimum high-level output voltage under a specified source current; VOL,max is the guaranteed maximum low-level output voltage under a specified sink current. VIH,min is the minimum input voltage guaranteed to be recognized as high; VIL,max is the maximum input voltage guaranteed to be recognized as low. The region between these two thresholds is typically an undefined logic region, not a third usable state.

With a common reference ground and under corresponding operating conditions, the static noise margins are NMH = VOH,min − VIH,min and NML = VIL,max − VOL,max. For example, if the transmitter guarantees high ≥ 2.9 V and low ≤ 0.2 V, and the receiver requires high ≥ 2.0 V and low ≤ 0.8 V, the margins on both sides are 0.9 V and 0.6 V, respectively. If another receiver has a high threshold of 3.5 V, the high-level margin becomes −0.6 V, functionality is not guaranteed, and one cannot substitute the worst-case budget with "measured no-load voltage is 3.3 V."

TTL and CMOS are logic implementation/family backgrounds; they do not yield a unique threshold table solely based on supply voltage. Both HC and HCT belong to the CMOS family, but HCT inputs are designed to be compatible with TTL thresholds. The VIH of different low-voltage families cannot be uniformly written as 0.7VCC or 2.0 V. Outputs that "go almost to the rail" generally depend on very light loads; under load, one must check the corresponding current conditions. Nexperia: 74HC/HCT00 Electrical Characteristics

Connection checks must also cover both directions and power-down states. A pin tolerant to 5 V might only apply to specific input modes or supply conditions; another input without overvoltage tolerance might back-power an unpowered supply through protection diodes. Current-limiting resistors can limit current, but they are not level shifters that are legal under all circumstances. Operating conditions, absolute maximum ratings, and long-term reliable use conditions should be read separately.

Why Push-Pull, Open-Drain, and Tri-State Cannot Be Arbitrarily Interconnected

Push-pull outputs actively drive both high and low. If two push-pull outputs are connected directly with one high and one low, a contention current is formed; even if they can temporarily output the same level, this does not prove safety under all states. Tri-state outputs add a high-impedance Z state, suitable for shared buses, but the protocol must ensure that drivers are not active simultaneously during handover, and the level during the high-impedance period must be determined by bias or bus-hold mechanisms.

Open-drain only actively pulls low; upon release, the level is restored to high by a pull-up resistor. Multiple compatible open-drain outputs can share a single line; if any end pulls low, the bus is low. In positive logic, this is called wired-AND; in low-active request semantics, it often manifests as "any request is valid." The pull-up supply must be within the allowed range of all connected pins and cannot be arbitrarily replaced with a higher voltage.

The smaller the pull-up resistor, the larger the low-level sink current; the larger the resistor, the slower the rise. For lumped RC and 30%–70% rise time, tr ≈ 0.8473 Rp Cb. Assuming a pull-up of 3.3 V, VOL,max = 0.4 V, allowed sink current of 3 mA, total capacitance of 100 pF, and a rise budget of 300 ns, the lower limit for Rp is approximately 967 Ω, and the upper limit is approximately 3.54 kΩ. A nominal 2.2 kΩ corresponds to approximately 1.32 mA and 186 ns; however, one must also check supply, resistor, capacitor, and device tolerances. Resistor Chapter: Pull-up Budget

Differential Signals Suppress Common-Mode Noise, But Do Not Provide Electrical Isolation

Let Vdiff = V+ − V− and Vcm = (V+ + V−) / 2, both expressed with respect to the receiver's reference ground. If both wires increase by the same voltage, the ideal difference remains unchanged, but the common-mode voltage still changes. The receiver can only maintain functionality within its specified common-mode input range; a differential structure does not automatically isolate ground potential differences, nor does it guarantee the elimination of ground loops.

Taking typical LVDS as an example, 1.375 V and 1.025 V form a 350 mV differential and 1.2 V common-mode; after both lines rise by 0.5 V, the differential remains 350 mV, and the common-mode becomes 1.7 V. Whether this is still valid depends on checking the receiver's range, not just looking at the difference. Asymmetric coupling between lines can convert common-mode interference into differential-mode interference, and the receiver's common-mode rejection is also limited. TI: LVDS Signal Basics

Symmetric routing of twisted pairs or differential pairs can reduce unbalanced coupling and radiation, but return paths, reference planes, connectors, and shielding still require design. Non-isolated long-line systems must control ground potential differences and reference connections; isolated systems require matching isolated transceivers, isolated power supplies, and interface-side references. Do not arbitrarily short all device grounds, nor assume that two differential wires naturally solve all grounding issues.

Same difference, why can reception fail?

Changing common mode moves the dot along one diagonal without changing the difference. Outside the assumed range, the model withdraws the guarantee. Real devices also require pin-voltage, rejection and electrical checks.

Physical Layer Quick Reference: Digital Protocols Do Not Replace Transceivers

There is no unified "max MHz / max meters" because these are not constants determined by logic levels alone. Propagation loss, edge rates, devices, cables, encoding, and topology jointly limit the system. Lower bit rates may also use fast edges, still causing reflections and EMI.

LVDS, D-PHY, and USB Cannot Be Interchanged Just Because "They Are All Differential"

Typical LVDS differential voltage switches between +350 mV and −350 mV, with a differential peak-to-peak of approximately 700 mV; this number is not the same concept as the swing of each line to ground. The 100 Ω termination consumes I²R ≈ 1.225 mW, which is only the power on the termination, not the complete driver power consumption.

MIPI D-PHY defines its own high-speed differential and low-power operating mechanisms; one cannot simply connect a standard LVDS driver and assume compatibility. USB also has specific state detection and electrical modes; USB 2.0 Low/Full/High speed cannot be summarized by a single "±400 mV." Protocol bridging, electrical conversion, and connector adaptation are different problems. MIPI: D-PHY

RS-232: UART Pins Are Not RS-232 Voltages

Common asynchronous serial data on the RS-232 side represents logic 1 with negative voltage and logic 0 with positive voltage; the receiver's range of approximately −3 to +3 V does not guarantee valid decision. The UART pin side typically uses non-inverted CMOS logic and must undergo voltage and polarity conversion via a suitable RS-232 transceiver. Devices like the MAX3232 use charge pumps to generate the required voltages; check the specific model for operating supply and speed; 115.2 kbit/s is a common configuration, not the absolute upper limit for the entire RS-232 family. TI: MAX3232

In the common PC DTE DE-9 interface, pin 2 is RXD, pin 3 is TXD, and pin 5 is Signal Ground; the DCE end has opposite directions, and devices may also use custom interfaces. Check the direction and pinout against the device pin table before connecting; do not cross-wire based solely on connector shape.

RS-485: 32 Is the Unit Load Budget, Not a Fixed Node Count

RS-485 specifies only the electrical layer; frame format, addressing, and access scheduling are determined by upper-layer protocols. Standard-compliant receivers commonly have common-mode requirements of −7 to +12 V; under specified loads, the driver must provide at least 1.5 V differential, and the receiver decision is approximately ±200 mV; specific extended ranges depend on the device datasheet. 32 unit loads is an electrical load budget; 1/8 UL receivers can theoretically reach 256 nodes under ideal load accounting, but bias, cable capacitance, stubs, and protocols still limit the actual node count. TI: RS-485 Design Guide

A typical half-duplex bus uses a trunk and short stubs, with termination at both ends of the trunk according to the cable's differential impedance, commonly 120 Ω each. These two resistors appear as 60 Ω to the driver, plus receiver and bias loads; installing 120 Ω at every node would severely overload the bus. Whether termination can be omitted under electrically short lines and slow edges requires analysis of propagation time and waveforms; it cannot be determined solely by low baud rate.

When all drivers release, a defined idle receive state is still required, achieved by transceiver failsafe or appropriate external bias. The A/B naming is mixed between devices; polarity must be confirmed via truth tables and measurements. The send control DE must cover the time until the last stop bit is truly transmitted, not just wait for the software send queue to be empty; additionally, time must be left for the other party to switch direction.

CAN: Transceivers Provide Dominant/Recessive, Controllers Handle Arbitration and Frame Processing

In high-speed CAN, the differential is close to 0 during recessive, and CANH rises while CANL falls during dominant. Multiple nodes can perform bit-by-bit arbitration according to the rule that dominant overrides recessive, but CRC, retransmission, error counting, and bus-off are mainly handled by the CAN controller/protocol and cannot rely solely on a single transceiver for complete CAN communication.

Classic CAN and CAN FD have different arbitration/data phase rates; the data phase capability of FD is also limited by the transceiver, topology, and bit timing. A model supporting 5 or 8 Mbit/s does not mean all FD networks can run at that speed. The common 120 Ω termination at both ends applies to the high-speed CAN discussed here and cannot be applied to all fault-tolerant or single-wire CAN physical layers. TI: TCAN1042 Series

Level Shifting Must Match Drive Method

Resistive dividers are suitable for unidirectional signals with a calculated budget. Assuming an ideal input source and negligible receiver leakage, 5 V through an upper arm of 10 kΩ and a lower arm of 20 kΩ yields 3.333 V; but if the input rises to 5.25 V, the output becomes 3.5 V, not yet accounting for tolerance and overshoot. The divider source impedance is 10k ∥ 20k ≈ 6.67 kΩ, forming a low-pass filter with input/tracing capacitance; it cannot boost voltage, nor is it a bidirectional push-pull converter.

Dedicated dual-supply converters require checking direction control, I/O structure, load, power-up sequence, and output enable. The TXB0104 is an auto-direction device for push-pull interfaces and cannot be used for I²C open-drain buses just because it is "auto-direction"; the specific load and pull-up limits of the TXS family must also be checked by model. Auto-direction is not a classification standard for low-speed/high-speed. TI: TXB0104

Why the Gate of a Single MOS Bidirectional Open-Drain Converter Must Connect to the Low-Voltage Supply

The figure below shows a classic open-drain conversion structure: G is fixed to VLOW, S connects to the low-voltage side, D connects to the high-voltage side, and both sides have pull-ups. The diode in the figure represents the MOS internal body diode, not an additional external component.

When both sides are released, S ≈ VLOW, VGS ≈ 0, the transistor is off, and both sides rise to their respective supplies. When the low-voltage side pulls low, VGS increases, the channel conducts, and pulls the high-voltage side low as well. When the high-voltage side pulls low first, the body diode causes the low-voltage side to drop first, followed by VGS increasing to establish the channel, with both sides going low together. If G is incorrectly grounded, this normal turn-on mechanism does not hold. Nexperia: AN10441

One needs to select a MOSFET that turns on sufficiently at the actual low-side drive voltage and check VDS, VGS, parasitic capacitance, pull-ups, and power-down behavior at each end. When both sides are low, a device pulling low may need to withstand the sum of pull-up currents from both sides; do not select sink current capacity based only on the local pull-up. This structure is not an isolator and is not suitable for arbitrary high-speed push-pull or arbitrary power-up sequences.

Re-calculatable Connection Budgets

from math import isclose

assert isclose(2.9-2.0, 0.9)
assert isclose(0.8-0.2, 0.6)
assert 2.9-3.5 < 0  # High-level functionality not guaranteed

vp, vn = 1.375, 1.025
assert isclose(vp-vn, (vp+0.5)-(vn+0.5))
assert isclose((vp+vn)/2+0.5, 1.7)

rmin = (3.3-0.4)/0.003
rmax = 300e-9/(0.8473*100e-12)
assert rmin < 2200 < rmax
assert isclose(0.8473*2200*100e-12, 186.406e-9)
assert isclose(1/(1/120+1/120), 60)
assert isclose(0.0035**2*100, 0.001225)
assert isclose(5.25*20000/(10000+20000), 3.5)
print('Static margin, common-mode, pull-up, termination, and divider budget checks passed')

The examples use explicit assumptions and verify calculation relationships; real connections also require checking against electrical manuals and corresponding load waveforms.

Continue Reading

• Serial Bus Protocols: Timing and access rules for UART, SPI, I²C, etc.
• USB and Type-C: Interface shapes, data capabilities, and power negotiation.
• PCB Design Fundamentals: Impedance, reference planes, and return paths.